Illustratively, the substrate is p-type and the source and drain are N.sup.+. A gate oxide 104 is fashioned over the substrate a hundred and the source 102 and drain 103. A floating gate 105 is disposed on the gate oxide 104, situated over the channel a hundred and one.
DETAILED DESCRIPTION OF THE PRESENT INVENTIONA flash memory structure of the present invention is illustrated in FIG. This structure includes a substrate 200 of a primary dopant kind. For instance, the substrate could be P-type silicon with a doping concentration of about 5E15/cm.sup.three. A supply 203 and a drain 204 of a second dopant kind are shaped within the substrate with a channel 205 fashioned between them. The second dopant kind, for example, is N.sup.+ -type.
A control gate 130 is fashioned over the insulating layer 120. 3, the oxidized silicon construction is annealed in a N.sub.2 ambiance. The annealing forms a layer 60 of silicon enriched oxide (“Si–O”), having a thickness of roughly between a hundred .ANG. This Si–O layer 60 enhances the tunneling.
The means of declare 1, whereby mentioned O2 penetrates into mentioned silicon substrate to a depth of a minimum of a hundred Å to ensure formation of mentioned silicon enriched wealthy oxide layer. The ion implantation dose of arsenic ions happens at roughly 50 kev and a dose unit of roughly 12700 yen to usd 5.0E15/cm2. 3, the oxidized silicon construction is annealed in a N2 atmosphere. The annealing types a layer 60 of silicon enriched oxide (“Si–O”), having a thickness of roughly between 100 Å and 200 Å. The annealing takes place at a temperature of about 750° C.˜950° C.
A layer of silicon enriched oxide 201 is formed on the floor of the substrate 200. A gate oxide 208 is formed over the silicon enriched oxide layer 201. A floating gate 207 is shaped over the channel 205. The floating gate 207 may be shaped by a layer of polysilicon having a thickness of roughly a thousand .ANG..
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The similar quantity of F-N tunneling current will happen at a lot decrease voltage for the creative SiO2 +Si–O construction as in contrast with that of a traditional SiO2 structure. Higher current injection efficiency for SiO2 +Si–O layer is due to larger electrical field on the surface of silicon islands in the Si–O layer. Therefore, in Flash EEPROM purposes, both the programming and erase voltage could be reduced through the use of the SiO2 +Si–O construction and process of the present invention. In present flash reminiscence cells, thermal oxide is often used as a tunnel dielectric. The magnitude of the tunneling present is proscribed by the maximum field which could be utilized to the oxide without considerably degrading its high quality.
This performance is essential for purposes and services that drive the demand for IP addresses. 3, a brand new layer of SiO.sub.2 50 is grown on the floor. The SiO.sub.2 layer 50 is grown to a thickness of approximately a hundred .ANG. This oxidation course of will partially oxidize the oxygen-implanted silicon forty. three, a new layer of SiO2 50 is grown on the surface.
The process of declare 1, wherein said second SiO.sub.2 layer is grown by thermal oxidation. The means of declare 1, whereby said second SiO2 layer is grown by thermal oxidation. 4 illustrates the traits of the F-N tunneling current for the current invention. The means of declare 1, whereby said annealing takes place at a temperature of approximately 750.diploma.
